ATJ2085 DMA
From S1MP3 Wiki
DMA stands for "direct memory access" The atj8085 has 2 unknown (most likely identical) DMA controllers
Contents |
Summary
The following summary is based on ongoing reverse engineering done for s1mulator, and is incomplete.
Connectivity
The DMA is connected via 12 ports to the Z80 core (see port map at bottom of this page), and it has full memory access, with its own bank select lines.
Addressing
The Source and destination REGS are the same format (i.e. flip the values to reverse the transfer), both are 5 bytes wide. The first 2 address REGs make up a 16bit address, with 0 starting at the bottom of the selected memory bank.
The last 2 (possibly 3) Address REGS act as memory bank select values, known bank values (or in some cases just masks) are:
| address 3 | address 4 | bank |
|---|---|---|
| 0x84 | 0x00 | NAND chip 1 |
| 0x88 | 0x00 | NAND chip 2 |
| 0x00 | 0x80 | ZRAM1 |
| 0x40 | 0x?7 | ZRAM2 |
| 0x40 | ???101?? | Hi IDM |
| 0x40 | ???001?? | Low IDM |
| 0x40 | ???100?? | Hi IPM |
| 0x40 | ???000?? | Low IPM |
? means unknowen bit or bits
Counter
16bit counter value, it is 1 less than the number of bytes copied (ie 0x1ff copies 0x200 bytes)
Mode
So far, all I've found is mode 0xc0, which seams to copy, without triggering an interrupt when it is finished. It Increased both src and dst addresses.
Command
Send command 0x01 to start copying, changes back to 0 (or bit 0 = 0) when copy is finished.
Port Map
;-----------------------------------------------------------------------------*/ ;DMA1 CNTRL ;-----------------------------------------------------------------------------*/ DEFC DMA1_SRCADDR0_REG = (0x06) DEFC DMA1_SRCADDR1_REG = (0x07) DEFC DMA1_SRCADDR2_REG = (0x08) DEFC DMA1_SRCADDR3_REG = (0x09) DEFC DMA1_SRCADDR4_REG = (0x0a) DEFC DMA1_IPMSRC_REG = (0x0a) DEFC DMA1_IDMSRC_REG = (0x0a) DEFC DMA1_ZRAM2SRC_REG = (0x0a) DEFC DMA1_DSTADDR0_REG = (0x0b) DEFC DMA1_DSTADDR1_REG = (0x0c) DEFC DMA1_DSTADDR2_REG = (0x0d) DEFC DMA1_DSTADDR3_REG = (0x0e) DEFC DMA1_DSTADDR4_REG = (0x0f) DEFC DMA1_IPMDST_REG = (0x0f) DEFC DMA1_IDMDST_REG = (0x0f) DEFC DMA1_ZRAM2DST_REG = (0x0f) DEFC DMA1_CNTR_LO_REG = (0x10) DEFC DMA1_CNTR_HI_REG = (0x11) DEFC DMA1_MODE_REG = (0x12) DEFC DMA1_COMMAND_REG = (0x13) ;-----------------------------------------------------------------------------*/ ;DMA2 CNTRL ;-----------------------------------------------------------------------------*/ DEFC DMA2_SRCADDR0_REG = (0x14) DEFC DMA2_SRCADDR1_REG = (0x15) DEFC DMA2_SRCADDR2_REG = (0x16) DEFC DMA2_SRCADDR3_REG = (0x17) DEFC DMA2_SRCADDR4_REG = (0x18) DEFC DMA2_IPMSRC_REG = (0x18) DEFC DMA2_IDMSRC_REG = (0x18) DEFC DMA2_ZRAM2SRC_REG = (0x18) DEFC DMA2_DSTADDR0_REG = (0x19) DEFC DMA2_DSTADDR1_REG = (0x1a) DEFC DMA2_DSTADDR2_REG = (0x1b) DEFC DMA2_DSTADDR3_REG = (0x1c) DEFC DMA2_DSTADDR4_REG = (0x1d) DEFC DMA2_IPMDST_REG = (0x1d) DEFC DMA2_IDMDST_REG = (0x1d) DEFC DMA2_ZRAM2DST_REG = (0x1d) DEFC DMA2_CNTR_LO_REG = (0x1e) DEFC DMA2_CNTR_HI_REG = (0x1f) DEFC DMA2_MODE_REG = (0x20) DEFC DMA2_COMMAND_REG = (0x21)
