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Generally, any Z80 processor supports maskable and non-maskable interrupts. The CPU always accepts a NMI. When this occurs, the CPU ignores the next instruction that it fetches and instead performs a restart to location 0x0066. The CPU functions as if it had recycled a restart instruction, but to a location other than one of the eight software restart locations. A restart is merely a call to a specific address in page 0 of memory.

For maskable interrupts, the CPU can be programmed to respond in any one of three possible modes:

  • Mode 0

With this mode, the interrupting device can place any instruction on the data bus and the CPU executes it. Thus, the interrupting device provides the next instruction to be executed. Often this is a restart instruction because the interrupting device only need supply a single byte instruction.

  • Mode 1

When this mode is selected by the programmer, the CPU responds to an interrupt by executing a restart to location 0x0038. Thus, the response is identical to that for a non-maskable interrupt except that the call location is 0x0038 instead of 0x0066.

  • Mode 2

This mode is the most powerful interrupt response mode. With a single 8-bit byte from the user, an indirect call can be made to any memory location. In this mode, the programmer maintains a table of 16-bit starting addresses (interrupt vector table) for every ISR. This table may be located anywhere in memory. When an interrupt is accepted, a 16-bit pointer must be formed to obtain the desired interrupt service routine starting address from the table. The upper eight bits of this pointer is formed from the contents of the I register. The I register must be loaded with the applicable value by the programmer before. A CPU reset clears the I register so that it is initialized to zero. The lower eight bits of the pointer must be supplied by the interrupting device. Only seven bits are required from the interrupting device because the least-significant bit must be a zero. This is required because the pointer is used to get two adjacent bytes to form a complete 16- bit service routine starting address and the addresses must always start in even locations.

Interrupts mode2.gif

The first byte in the table is the least-significant (low order portion of the address). The programmer must complete this table with the correct addresses before any interrupts are accepted. The programmer can change this table by storing it in Read/Write Memory, which also allows individual peripherals to be serviced by different service routines. When the interrupting device supplies the lower portion of the pointer, the CPU automatically pushes the program counter onto the stack, obtains the starting address from the table, and performs a jump to this address. The Z80 peripheral devices include a daisy-chain priority interrupt structure that automatically supplies the programmed vector to the CPU during interrupt acknowledge.

List of interrupts

  • 0x0000..0x0038 - software restart locations
  • 0x0036 - entrypoint for any maskable interrupt (mode 1)
  • 0x0066 - entrypoint for any non-maskable interrupt
  • 0xII56 - interrupt vector of usb controller (mode 2)