NAND controller

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The NAND controller sits between the NAND chip and the rest of the SoC.

Contents

ATJ2085

These are the ports for the for the 208x chips.

port number register name
0x28 NAND_ENABLE_REG
0x29 NAND_CEMODE_REG
0x2A NAND_CMD_REG
0x2B NAND_CA_REG
0x2C NAND_RA_REG
0x2D NAND_BA_REG1
0xEC NAND_BA_REG2
0xCC NAND_ECCCTRL_REG
0xCD NAND_ECC_REG0
0xCE NAND_ECC_REG1
0xCF NAND_ECC_REG2

ATJ209x

Between the 208x and 209x series, the NAND controller changed significantly. The ability to control the ALE and CLE lines and directly issue flash commands is gone, replaced with a controller that also integrates DMA and ECC functionality. It is still possible to read/write data by accessing the external memory space (>=8000h), but it is simpler and faster to use the integrated DMA controller, except for special purposes. This is also required for use of the ECC hardware.

Ports

  • 28 - NAND Controller Status and CE Enable
    • 7 - reserved
    • 6 - Data Ready IRQ enable
      • Not used in FLASHLDR nor BREC. Maybe ACTOS' driver uses it.
    • 5 - CE4 Enable
    • 4 - CE3 Enable
    • 3 - CE2 Enable
    • 2 - CE1 Enable
    • 1 - CE Enable Enable
      • When 0, the CE signals are controlled by port 2 (external memory address) and activate only when reading/writing to external memory.
      • When 1, bits 2-5 control their respective CE signals directly. This is needed for the NAND controller to work. (Either because it can't issue address/command cycles, or because "CE-don't-care" mode requires setup and hold times that can't be satisfied.)
    • 0 - Controller status. 0 = idle, 1 = busy.
  • 29 - NAND Status and Controller Configuration
    • 7 - Data Ready IRQ pending
      • This bit is set to 1 when R/B returns to 1 from 0 (and an IRQ will be triggered if enabled.) Write 1 to clear.
    • 6 - R/B input from IC pin. Since NAND's R/B outputs are open-drain, multiple chips can be connected together along with a pullup resistor for wired-OR sensing of busyness.
    • 5 - DMA Finished
      • Set to 1 when the DMA controller finishes a transfer. Writing 1 will clear it, and so will issuing another command to the controller.
    • 4:3 - DMA Wait State Select
      • Select 0 to 3 wait states when the DMA controller accesses the flash. At 24MHz (default DMA clock), the cycle time is 41.7ns which is too fast for some flash. FLASHLDR sets this to 2 wait states which gives a more generous 125ns cycle time.
    • 2 - DMA Wait State RD/WR Level Select
      • 0 - WE or RE is 1 during wait states
      • 1 - WE or RE is 0 during wait states
      • Normal operation requires this set to 1 so that the read/write lines will not be returned to 1 too quickly
    • 1:0 - Address Cycle Select
      • 00 - 5 cycles
      • 01 - 4 cycles
      • 10 - 3 cycles
      • 11 - reserved
      • Configures the number of address cycles issued.
  • 2A - NAND Controller Command
    • Commands written to this port are immediately executed. See below for descriptions.
  • 2B - Address Register and ECC Select
    • 7:6 - Bits 5:4 of address registers to select
      • 00=0x3FC0-0x3FCF, 01=0x3FD0-0x3FDF, etc.
    • 5 - reserved, should be 0
    • 4 - "User ECC storage control bit" need to analyze ECC more to figure this one out
    • 3:2 - ECC type
      • Available options are 128/20, 256/22, 512/24, and 2K/28 (bytes/ECC bits)
    • 1 - "ECC Storage Select" need to analyze ECC more to figure this one out
    • 0 - 1-bit ECC enable
      • 1-bit ECC is used for SLC flash only and can correct only single-bit errors.
  • 2C - User ECC0 need to figure out what 'user' means
  • 2D - User ECC1
  • CC - ECC0
  • CD - ECC1
  • CE - ECC2
  • CF - ECC3, ECC Status, and Test Mode
    • 7 - ECC Error
      • Set to 1 if an ECC error was detected. Write 1 to clear.
    • 6 - User ECC Error need to figure out what 'user' means
      • Set to 1 if a user ECC error was detected. Write 1 to clear.
    • 5 - NAND Flash Test Enable
      • Probably shouldn't touch this bit.
    • 4 - NAND Flash State Machine Reset
      • Write 0 to reset the controller. Set back to 1 for proper operation.
    • 3:0 - ECC bits
  • E8 - RS Error FIFO
    • 16-byte-deep FIFO for error locations and values. Usage described below.
  • E9 - RS Parity FIFO
    • 9-byte-deep FIFO for the RS parity bytes. Usage described below.
  • EA - ECC4 Test Register
    • Probably shouldn't touch this.
  • EB - RS Status and Configuration
    • 7 - More than 3 errors
      • Set to 1 when there are more than 3 errors detected. Write 1 to reset.
      • This may be used to perform "weak block" detection.
    • 6 - Uncorrectable
      • Set to 1 when there are more than 4 errors detected (uncorrectable). Write 1 to reset.
    • 5 - reserved
    • 4 - Error
      • Set to 1 when there are more than 0 errors detected. Write 1 to reset.
    • 3 - FIFO Ready
      • Set to 1 once the RS encoder/decoder is finished.
    • 2 - FIFO Pointer Reset
      • Write 1 to reset the FIFOs (E8 and E9). Write 0 to resume normal operation.
    • 1 - Auto-write RS Parity
      • Set to 1 to disable automatically writing the parity bytes by the DMA controller upon a write.
    • 0 - RS ECC Enable
      • RS ECC is used for MLC and can correct up to 4 9-bit error bursts.

Address Registers

The address registers are at a 64-byte area at the end of ZRAM1, 0x3FC0-0x3FFF. This consists of 4 16-byte register banks; the one to use is selected by the top 2 bits of port 2B.

offset use Sent in 5-cycle mode Sent in 4-cycle mode Sent in 3-cycle mode
0 Address cycle 0 - column[7:0] x x x
1 Address cycle 1 - column[15:8] (LB only, not sent for SB) x - -
2 Address cycle 2 - row[7:0] x x x
3 Address cycle 3 - row[15:8] x x x
4 Address cycle 4 - row[23:16] x x -
5-6 DMA memory offset
7 DMA memory page, sector size, and direction
8-F for spare bytes

Commands

Written to port 2A to initiate an operation.

  • 00 READ_0
    • Command 00 is sent to the flash, followed by the configured number of address cycles.
    • Used for reading the first 256 bytes in a sector for small-block devices, and to initiate a page read for large-block devices.
    • The DMA and ECC features are not used.
  • 01 SB_READ_1
    • Command 01 is sent ot the flash, followed by the configured number of address cycles.
    • Used for reading bytes 256-511 in a sector for small-block devices, not applicable to large-block.
    • The DMA and ECC features are not used.
  • 10 WRITE_CONFIRM
    • Command 10 is sent to the flash, which initiates the page programming process.
  • 30 LB_READ_2
    • Command 30 is sent to the flash.
    • Begins the actual read operation for a large-block device.
    • The DMA and ECC features are not used.
  • 50 SB_READ_2
    • Command 50 is sent to the flash, followed by the configured number of address cycles.
    • Used for reading bytes 512-527 (spare area) in a sector for small-block devices, not applicable to large-block.
    • The DMA and ECC features are not used.
  • 60 ERASE
    • Command 60 is sent to the flash, followed bythe configured number of address cycles.
  • 70 READ_STATUS
    • Command 70 is sent to the flash.
    • Reads from extended memory obtain the status register value.
  • 80 WRITE
    • Command 80 is sent to the flash, followed by the configured number of address cycles.
    • The DMA and ECC features are not used.
  • 90 READ_ID
    • Command 90 is sent to the flash.
    • Reads from extended memory obtain the identification bytes.
  • ED SB_READ_DMA
    • Commands 00 or 01 are sent to the flash depending on the address requested
    • The configured number of address cycles are issued
    • Once the flash is ready, DMA is initiated to transfer the requested amount
    • If RS or 1-bit ECC is enabled, ECC hardware performs verification on the data
  • D0 ERASE_CONFIRM
    • Command D0 is sent to the flash, which initiates the block erase process.
  • F7 LB_READ_DMA_2
    • Command 05 is sent to the flash, followed by the configured number of address cycles.
    • Command E0 is sent to the flash
    • The requested number of bytes are read from the flash via DMA
    • If RS or 1-bit ECC is enabled, ECC hardware performs verification on the data
    • This command is valid only after FB is issued, since the page register in the flash has to be read first.
    • By not issuing a second internal read operation to the flash, this command improves performance when reading other bytes in the same page. FLASHLDR does not use it, but BREC does.
  • FA LB_READ_DMA_3
    • Command 05 is sent to the flash, followed by address cycles to access the corresponding spare area
    • Command E0 is sent to the flash
    • The spare bytes are read from the flash via DMA
    • This command is valid only after FB is issued, since the page register in the flash has to be read first.
  • FB LB_READ_DMA_1
    • Command 00 is sent to the flash, followed by the configured number of address cycles.
    • Command 30 is sent to the flash
    • The requested number of bytes are read from the flash via DMA
    • If RS or 1-bit ECC is enabled, ECC hardware performs verification on the data
  • FC LB_WRITE_DMA_3
    • Command 85 is sent to the flash, followed by address cycles to access the corresponding spare area
    • The spare bytes, including the ECC calculated, is sent to the flash
  • FD LB_WRITE_DMA_2
    • Command 85 is sent to the flash, followed by the configured number of address cycles.
    • The DMA controller transfers the specified number of bytes
    • If enabled, ECC is calculated on the bytes transferred
  • FE LB_WRITE_DMA_1
    • Command 80 is sent to the flash, followed by the configured number of address cycles.
    • The DMA controller transfers the specified number of bytes
    • If enabled, ECC is calculated on the bytes transferred
  • FF RESET
    • Sends FF to the flash, resetting it, and the flash controller as well.
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